The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a metal oxide semiconductor (MOS) transistor of high breakdown voltage having a triple diffused drain and a method for manufacturing the same.
As an example of a semiconductor device which requires a high breakdown voltage and a low resistance is a driver integrated circuit (hereinafter, referred to as a driver IC) used for a liquid crystal display element. The driver IC requires a high breakdown voltage, a high operating voltage, a high current drive capability and a low on-state resistance because it operates by being connected to peripheral equipments.
To satisfy these requirements, the driver IC is designed to have a diffusion layer of a high resistance doped with low concentration impurity. As the concentration of the impurities doped into the diffusion layer lowers, the breakdown voltage becomes higher, but the current drive capability and the operating voltage become lower. Also, a diffusion layer having a low concentration of impurities induces an increase in the operating resistance (R.sub.ON), which causes a problem in that the size of a chip may be increased.
Double diffused MOS (DMOS), or a metal oxide semiconductor field effect transistor (MOSFET) with a lightly doped drain (LDD) or double diffused drain (DDD) structure is used for an MOS transistor of high breakdown voltage. The DMOS has a structure which is considerably favorable for increasing the operating voltage. However, it is disadvantageous in that the size of chip is relatively large. It is difficult for a transistor with a DDD or LDD structure to obtain an adequate maximum operating voltage ((V.sub.op).sub.max).
To overcome these disadvantages, a complex diffused drain (hereinafter, referred to as CDD) structure in which an N source/drain (its impurity concentration is lower than N.sup.+, but higher than N.sup.-) is added to an N.sup.- source/drain and an N.sup.+ source/drain constituting a conventional DDD or a mask islanded DDD (MIDDD) is used to obtain a higher maximum operating voltage, a larger drain current (I.sub.ds current) and a lower operating resistance (R.sub.ON) than those of transistors with other structures when used in a chip of the same size.
FIG. 1 is a cross-sectional view of an MOS transistor of high breakdown voltage according to a conventional method disclosed in U.S. Pat. No. 4,990,982 (entitled "Semiconductor Device of High Breakdown Voltage", issued to Kayoko Omoto et al. on Feb. 5, 1992), which shows a CDD structure.
In FIG. 1, the reference numeral 10 denotes a semiconductor substrate, 12 denotes an N source, 14 denotes an N.sup.+ drain, 16 denotes a gate oxide film, 18 and 28 denote oxide films, 20 denotes a gate electrode, 22 denotes an N.sup.- drain, 24 denotes an N drain, 26 denotes an N.sup.- region, 30 denotes an interlayer insulation film, 32a and 32b denote contact holes, and 34a and 34b denote source and drain electrodes respectively.
To increase the maximum operating voltage of the CDD structure as shown in FIG. 1, the amount of ions implanted to the N.sup.- region should be increased, thereby decreasing the second peak value of the I.sub.SUb current, of which the limit is the drain breakdown voltage (BV.sub.dss),
Therefore, the transistor of a CDD structure having the N source/drain formed by additional ion implantation is developed so as to increase the maximum operating voltage by lowering the second peak value of I.sub.SUb current, while keeping the limit of BV.sub.dss value to an appropriate level.